In many fields of integrated circuit manufacturing, such as in the manufacture of dynamic random access memories (DRAMs) which use multiple levels of metal or polysilicon which have been photolithographically defined above the surface of a silicon substrate, it becomes necessary to provide certain different types of electrical connections between the various conductive levels and active or passive devices within an underlying substrate. For example, in the fabrication of DRAMs, it is customary to provide photolithographically defined word lines at one level within the integrated circuit structure and photolithographically defined bit or digit lines at another level within the integrated circuit structure. It is then also necessary to further provide certain vertical interconnects between the word and bit lines and certain devices such as access transistors fabricated within the silicon substrate.
In addition to the above requirements, there is also the requirement that electrical isolation be provided between the word and bit lines at certain locations and to provide electrical interconnections between the word and bit lines at certain other locations where it is desired to electrically join and connect a particular word line to a particular bit line or to a storage device such as a stacked capacitor in order to provide a desired read, write, or refresh data operation for the DRAM.
In the past, the above described electrical isolation between multi-level conductors in the integrated circuit was achieved by first defining an opening in one intermediate layer of conductor through which a vertical interconnection was provided between an upper layer conductor and a lower integrated circuit component without the vertical interconnect touching and shorting to the one intermediate conductive layer. Similarly, when it was desired to electrically connect an upper layer conductor to an intermediate conductive layer or to a lower device area within the integrated circuit, the patterns of metallization would be laterally spaced apart so that vias carrying the conductive interconnect from one layer would be laterally removed by a predetermined mask distance from the vias carrying the metallization interconnecting to an adjacent conductive layer.
The disadvantage with using both of the above electrical isolation and electrical interconnect techniques was that they impose an inherent photolithographic dimensional limitation on the maximum achievable packing density that can be obtained within the integrated circuit structure. It is the solution to this latter problem to which the present invention is directed.